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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 130 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers + Peripheral Control Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Non-volatile Program and Data Memories - 64K Bytes of In-System Reprogrammable Flash Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 2K Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 4K Bytes Internal SRAM - Up to 64K Bytes Optional External Memory Space - Programming Lock for Software Security - SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Two 8-bit PWM Channels - 6 PWM Channels with Programmable Resolution from 1 to 16 Bits - 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable Gain (1x, 10x, 200x) - Byte-oriented Two-wire Serial Interface - Dual Programmable Serial USARTs - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby - Software Selectable Clock Frequency - ATmega103 Compatibility Mode Selected by a Fuse - Global Pull-up Disable I/O and Packages - 53 Programmable I/O Lines - 64-lead TQFP and 64-pad MLF Operating Voltages - 2.7 - 5.5V for ATMEGA64L - 4.5 - 5.5V for ATMEGA64 Speed Grades - 0 - 8 MHz for ATMEGA64L - 0 - 16 MHz for ATMEGA64
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8-bit Microcontroller with 64K Bytes In-System Programmable Flash ATMEGA64 ATMEGA64L Preliminary
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2490F-AVR-12/03
Pin Configuration
Figure 1. Pinout ATMEGA64
TQFP/MLF
PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (IC3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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ATMEGA64(L)
2490F-AVR-12/03
(OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (IC1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10 PC1 (A9) PC0 (A8) PG1(RD) PG0(WR)
ATMEGA64(L)
Overview
The ATMEGA64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATMEGA64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
PF0 - PF7 PA0 - PA7 PC0 - PC7
VCC GND PORTF DRIVERS AVCC DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS PORTA DRIVERS PORTC DRIVERS
AGND AREF ADC INTERNAL OSCILLATOR CALIB. OSC
XTAL1
XTAL2 OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER
OSCILLATOR
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
TIMING AND CONTROL RESET
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
PEN
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
ALU
EEPROM
STATUS REGISTER
USART0
SPI
USART1
2-WIRE SERIAL INTERFACE
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. DATA DIR. PORTG REG. PORTG
+ -
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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2490F-AVR-12/03
The ATMEGA64 provides the following features: 64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel's high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATMEGA64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATMEGA64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
ATmega103 and ATMEGA64 Compatibility
The ATMEGA64 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATMEGA64. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (i.e., in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed. The ATMEGA64 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed circuit boards. The application note "Replacing ATmega103 by ATMEGA64" describes what the user should be aware of replacing the ATmega103 by an ATMEGA64.
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ATMEGA64(L)
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ATMEGA64(L)
ATmega103 Compatibility Mode By programming the M103C Fuse, the ATMEGA64 will be compatible with the ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATMEGA64 are not available in this compatibility mode, these features are listed below: * * * * * * * * One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. One 16 bits Timer/Counter with two compare registers instead of two 16 bits Timer/Counters with three compare registers. Two-wire serial interface is not supported. Port G serves alternate functions only (not a general I/O port). Port F serves as digital input only in addition to analog input to the ADC. Boot Loader capabilities is not supported. It is not possible to adjust the frequency of the internal calibrated RC Oscillator. The External Memory Interface can not release any Address pins for general I/O, neither configure different wait states to different External Memory Address sections. Only EXTRF and PORF exist in the MCUCSR Register. No timed sequence is required for Watchdog Timeout change. Only low-level external interrupts can be used on four of the eight External Interrupt sources. Port C is output only. USART has no FIFO buffer, so Data OverRun comes earlier. The user must have set unused I/O bits to 0 in ATmega103 programs.
* * * * * *
Pin Descriptions
VCC GND Port A (PA7..PA0) Digital supply voltage. Ground. Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATMEGA64 as listed on page 71. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATMEGA64 as listed on page 72.
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Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATMEGA64 as listed on page 75. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATMEGA64 as listed on page 76.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATMEGA64 as listed on page 79.
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input port only.
Port G (PG4..PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are Oscillator pins.
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ATMEGA64(L)
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ATMEGA64(L)
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 50. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF is the analog reference pin for the A/D Converter. This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation.
XTAL1 XTAL2 AVCC
AREF PEN
7
2490F-AVR-12/03
Register Summary
Address
(0xFF) .. (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61)
Name
Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved ADCSRB Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING PORTF DDRF
Bit 7
- - - - RXC1 RXCIE1 - - - - - - - - - - - - FOC3A COM3A1 ICNC3
Bit 6
- - - UMSEL1 TXC1 TXCIE1 - - - UMSEL0 - - - - - - - - FOC3B COM3A0 ICES3
Bit 5
- - - UPM11 UDRE1 UDRIE1 - - - UPM01 - - - - - - - - FOC3C COM3B1 -
Bit 4
- - - UPM10 FE1 RXEN1 - - - UPM00 - - - - - - - - - COM3B0 WGM33
Bit 3
- - - USBS1 DOR1 TXEN1
Bit 2
- - - UCSZ11 UPE1 UCSZ12
Bit 1
- - - UCSZ10 U2X1 RXB81
Bit 0
- - - UCPOL1 MPCM1 TXB81
Page
189 186 187 188 191 191
USART1 I/O Data Register
USART1 Baud Rate Register Low USART1 Baud Rate Register High - - USBS0 - - - - - - - - COM3C1 WGM32 - - UCSZ01 - - - - - ADTS2 - - COM3C0 CS32 - - UCSZ00 - - - - - ADTS1 - - WGM31 CS31 - - UCPOL0 - - - -
189
USART0 Baud Rate Register High - ADTS0 - - WGM30 CS30
191 247 136 131 134 136 136 137 137 137 137 137 137 138 138
Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte - - - - - FOC1A - - - - - FOC1B - - TICIE3 ICF3 - FOC1C - - OCIE3A OCF3A - - - - OCIE3B OCF3B - - - - TOIE3 TOV3 - - - - OCIE3C OCF3C - - - - OCIE1C OCF1C - -
139 140 135 137 137
Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte - - - TWINT TWA6 TWS7 - - - TWEA TWA5 TWS6 - - - TWSTA TWA4 TWS5 - - - TWSTO TWA3 TWS4 - - - TWWC TWA2 TWS3 - - - TWEN TWA1 - - - - - TWA0 TWPS1 - - - TWIE TWGCE TWPS0
205 207 207 206 205 40
Two-wire Serial Interface Data Register
Two-wire Serial Interface Bit Rate Register Oscillator Calibration Register - - XMBK - ISC31 - SPMIE - - - - - PORTF7 DDF7 - SRL2 - - ISC30 - RWWSB - - - - - PORTF6 DDF6 - SRL1 - - ISC21 - - - - - - - PORTF5 DDF5 - SRL0 - - ISC20 - RWWSRE - - PORTG4 DDG4 PING4 PORTF4 DDF4 - SRW01 - - ISC11 - BLBSET - - PORTG3 DDG3 PING3 PORTF3 DDF3 - SRW00 XMM2 - ISC10 - PGWRT - - PORTG2 DDG2 PING2 PORTF2 DDF2 - SRW11 XMM1 - ISC01 - PGERS - - PORTG1 DDG1 PING1 PORTF1 DDF1 XMM0 - ISC00 - SPMEN - - PORTG0 DDG0 PING0 PORTF0 DDF0 -
30 32 88 281
87 87 87 86 87
8
ATMEGA64(L)
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ATMEGA64(L)
Register Summary (Continued)
Address
(0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21)
Name
Reserved SREG SPH SPL XDIV Reserved EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE PINE
Bit 7
- I SP15 SP7 XDIVEN - ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0
Bit 6
- T SP14 SP6 XDIV6 - ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 - WGM00
Bit 5
- H SP13 SP5 XDIV5 - ISC61 INT5 INTF5 TICIE1 ICF1 SE - COM01
Bit 4
- S SP12 SP4 XDIV4 - ISC60 INT4 INTF4 OCIE1A OCF1A SM1 JTRF COM00
Bit 3
- V SP11 SP3 XDIV3 - ISC51 INT3 INTF3 OCIE1B OCF1B SM0 WDRF WGM01
Bit 2
- N SP10 SP2 XDIV2 - ISC50 INT2 INTF TOIE1 TOV1 SM2 BORF CS02
Bit 1
- Z SP9 SP1 XDIV1 - ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01
Bit 0
- C SP8 SP0 XDIV0 - ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00
Page
10 12 12 43 89 90 90 107, 138, 158 107, 140, 158 30, 44, 62 53, 256 102 104 104
Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register - COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - - COM1B0 WGM13 AS0 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10
105 131 134 136 136 137 137 137 137 138 138
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register IDRD/ OCDR7 - TSM - OCDR6 - - - OCDR5 - - - OCDR4 WDCE - - OCDR3 WDE ACME - OCDR2 WDP2 PUD OCDR1 WDP1 PSR0 OCDR0 WDP0 PSR321
155 157 158 253 55 70, 109, 143, 227 20 20 20
EEPROM Address Register High Byte
EEPROM Address Register Low Byte EEPROM Data Register - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE0 UDRIE0 ACO ADLAR ADATE - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE0 RXEN0 ACI MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL DOR0 TXEN0 ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0
20 85 85 85 85 85 85 85 85 86 86 86 86 167 167 165 186 187 188 191 228 243 245 246 246
SPI Data Register
USART0 I/O Data Register
USART0 Baud Rate Register Low
ADC Data Register High Byte ADC Data Register Low byte PORTE7 DDE7 PINE7 PORTE6 DDE6 PINE6 PORTE5 DDE5 PINE5 PORTE4 DDE4 PINE4 PORTE3 DDE3 PINE3 PORTE2 DDE2 PINE2 PORTE1 DDE1 PINE1 PORTE0 DDE0 PINE0
86 86 86
9
2490F-AVR-12/03
Register Summary (Continued)
Address
0x00 (0x20)
Name
PINF
Bit 7
PINF7
Bit 6
PINF6
Bit 5
PINF5
Bit 4
PINF4
Bit 3
PINF3
Bit 2
PINF2
Bit 1
PINF1
Bit 0
PINF0
Page
87
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
10
ATMEGA64(L)
2490F-AVR-12/03
ATMEGA64(L)
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k
Description
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
11
2490F-AVR-12/03
Instruction Set Summary (Continued)
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+ k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I 0 S1 S0 V1 V0 T1 T0 H1 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
12
ATMEGA64(L)
2490F-AVR-12/03
ATMEGA64(L)
Instruction Set Summary (Continued)
CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None None 1 1 1 N/A Clear Half Carry Flag in SREG H0 H 1
13
2490F-AVR-12/03
Ordering Information
Speed (MHz) 8 Power Supply 2.7 - 5.5 Ordering Code ATMEGA64L-8AC ATMEGA64L-8MC ATMEGA64L-8AI ATMEGA64L-8MI 16 4.5 - 5.5 ATMEGA64-16AC ATMEGA64-16MC ATMEGA64-16AI ATMEGA64-16MI Note: Package 64A 64M1 64A 64M1 64A 64M1 64A 64M1 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Type 64A 64M1 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)
14
ATMEGA64(L)
2490F-AVR-12/03
ATMEGA64(L)
Packaging Information
64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 64A B
R
15
2490F-AVR-12/03
64M1
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A 0.08 C
L D2
Pin #1 Corner
SIDE VIEW
1 2 3
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 b D D2 5.20 MIN 0.80 - 0.23 NOM 0.90 0.02 0.25 9.00 BSC 5.40 9.00 BSC 5.20 5.40 0.50 BSC 0.35 0.40 0.45 5.60 5.60 MAX 1.00 0.05 0.28 NOTE
E2
b
BOTTOM VIEW
e
E E2 e L
Notes: 1. JEDEC Standard MO-220, Fig. 1, VMMD.
01/15/03 TITLE 2325 Orchard Parkway 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm San Jose, CA 95131 Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. C
R
16
ATMEGA64(L)
2490F-AVR-12/03
ATMEGA64(L)
Erratas
ATMEGA64, all Rev.
The revision letter in this section refers to the revision of the ATMEGA64 device. There are no errata for this revision of ATMEGA64. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149.1; a logic one is scanned into the shift register instead of the TDI input while shifting the Device ID Register. Hence, captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during Update-DR. If ATMEGA64 is the only device in the scan chain, the problem is not visible. Problem Fix / Workaround Select the Device ID Register of the ATMEGA64 (Either by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller) to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. Issue the BYPASS instruction to the ATMEGA64 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATMEGA64. Note that the IDCODE instruction is the default instruction selected by the Test-Logic-Reset state of the TAP-controller. Alternative Problem Fix / Workaround If the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used), the boundary scan chain can be connected in such way that the ATMEGA64 is the fist device in the chain. UpdateDR will still not work for the succeeding devices in the boundary scan chain as long as IDCODE is present in the JTAG Instruction Register, but the Device ID registered cannot be uploaded in any case.
17
2490F-AVR-12/03
Datasheet Change Log for ATMEGA64
Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. Updated "Calibrated Internal RC Oscillator" on page 40.
1. Updated note in "XTAL Divide Control Register - XDIV" on page 43. 2. Updated "JTAG Interface and On-chip Debug System" on page 48. 3. Updated "Test Access Port - TAP" on page 248 regarding JTAGEN. 4. Updated description for the JTD bit on page 258. 5. Added a note regarding JTAGEN fuse to Table 119 on page 292. 6. Updated RPU values in "DC Characteristics" on page 326. 7. Updated "ADC Characteristics - Preliminary Data" on page 333. 8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in "Erratas" on page 17.
Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03
1. Added reference to Table 125 on page 296 from both SPI Serial Programming and Self Programming to inform about the Flash page size. 2. Added Chip Erase as a first step under "Programming the Flash" on page 323 and "Programming the EEPROM" on page 324. 3. Corrected OCn waveforms in Figure 52 on page 124. 4. Various minor Timer1 corrections. 5. Improved the description in "Phase Correct PWM Mode" on page 99 and on page 152. 6. Various minor TWI corrections. 7. Added note under "Filling the Temporary Buffer (Page Loading)" about writing to the EEPROM during an SPM page load. 8. Removed ADHSM completely. 9. Added note about masking out unused bits when reading the Program Counter in "Stack Pointer" on page 12. 10. Added section "EEPROM Write During Power-down Sleep Mode" on page 23. 11. Changed VHYST value to 120 in Table 19 on page 50.
18
ATMEGA64(L)
2490F-AVR-12/03
ATMEGA64(L)
12. Added information about conversion time for Differential mode with Auto Triggering on page 234. 13. Added tWD_FUSE in Table 129 on page 309. 14. Updated "Packaging Information" on page 15.
Changes from Rev. 2490B-09/02 to Rev. 2490C-09/02 Changes from Rev. 2490A-10/01 to Rev. 2490B-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad MLF Package and updated "Ordering Information" on page 14. 2. Added the section "Using all Locations of External Memory Smaller than 64 KB" on page 33. 3. Added the section "Default Clock Source" on page 36. 4. Renamed SPMCR to SPMCSR in entire document. 5. Added Some Preliminary Test Limits and Characterization Data Removed some of the TBD's and corrected data in the following tables and pages: Table 2 on page 22, Table 7 on page 36, Table 9 on page 38, Table 10 on page 38, Table 12 on page 39, Table 14 on page 40, Table 16 on page 41, Table 19 on page 50, Table 20 on page 54, Table 22 on page 56, "DC Characteristics" on page 326, Table 132 on page 328, Table 135 on page 331, Table 137 on page 334, and Table 138 - Table 145. 6. Removed Alternative Algortihm for Leaving JTAG Programming Mode. See "Leaving Programming Mode" on page 322. 7. Improved description on how to do a polarity check of the ADC diff results in "ADC Conversion Result" on page 242. 8. Updated Programming Figures: Figure 138 on page 294 and Figure 147 on page 307 are updated to also reflect that AVCC must be connected during Programming mode. Figure 142 on page 303 added to illustrate how to program the fuses. 9. Added a note regarding usage of the "PROG_PAGELOAD (0x6)" and "PROG_PAGEREAD (0x7)" instructions on page 314. 10. Updated "Two-wire Serial Interface" on page 196. More details regarding use of the TWI Power-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added the note at the end of the "Bit Rate Generator Unit" on page 202. Added the description at the end of "Address Match Unit" on page 203. 11. Updated Description of OSCCAL Calibration Byte. In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: 19
2490F-AVR-12/03
Improved description of "Oscillator Calibration Register - OSCCAL(1)" on page 40 and "Calibration Byte" on page 293. 12. When using external clock there are some limitations regards to change of frequency. This is descried in "External Clock" on page 41 and Table 132 on page 328. 13. Added a sub section regarding OCD-system and power consumption in the section "Minimizing Power Consumption" on page 47. 14. Corrected typo (WGM-bit setting) for: - - - - "Fast PWM Mode" on page 97 (Timer/Counter0). "Phase Correct PWM Mode" on page 99 (Timer/Counter0). "Fast PWM Mode" on page 150 (Timer/Counter2). "Phase Correct PWM Mode" on page 152 (Timer/Counter2).
15. Corrected Table 81 on page 190 (USART). 16. Corrected Table 103 on page 262 (Boundary-Scan)
20
ATMEGA64(L)
2490F-AVR-12/03

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